View ML4821_157485.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.fairchildsemi.com
ML4821
Power Factor Controller
Features
* Average current sensing for lowest possible harmonic distortion * Average line compensation with brown-out control * Precision buffered 5V reference * 1A peak current totem-pole output drive * Overvoltage comparator eliminates output "runaway" due to load removal * Wide common mode range in current sense comparators for better noise immunity * Large oscillator amplitude for better noise immunity * Output driver internally limited to 17V * "Sleep mode" shutdown input
General Description
The ML4821 provides complete control for a "boost" type power factor correction system using the average current sensing method. Special care has been taken in the design of the ML4821 to increase system noise immunity. The circuit includes a precision reference, gain modulator, average current error amplifier, output error amplifier, over-voltage protection comparator, shutdown logic, as well as a high current output. In addition, start-up is simplified by an undervoltage lockout circuit. In a typical application, the ML4821 controls the AC input current by adjusting the pulse width of the output MOSFET. This modulates the line current so that its shape conforms to the shape of the input voltage. The reference for the current regulator is a product of the sinusoidal line voltage times the output of the error amplifier which is regulating the output DC voltage. Average line voltage compensation is provided in the gain modulator to ensure constant loop gain over a wide input voltage range. This compensation includes a special "brown-out" control which reduces output power below 90V RMS input.
Block Diagram
11 OVP ILIM VREF
+ -
0.7V
+ -
1
- +
SLEEP UNDER VOLTAGE LOCKOUT
VREF
16
2
IA OUT IA-
GND
18
3
- - +
IA+ R S Q VLIMIT 17V
VCC
15
+
4
OUT
14
5
ISINE VRMS
OUT GAIN MODULATOR
PGND RT OSC SYNC CT VREF
13 12 10 17
8
6
EA OUT
7
EA- VREF SOFT START
- +
9
REV. 1.0.2 6/19/01
ML4821
PRODUCT SPECIFICATION
Pin Connection
18-Pin PDIP (P18)
ILIM IA OUT IA- IA+ ISINE EA OUT EA- VRMS SOFT START
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
20-Pin SOIC (S20)
GND CT VREF VCC OUT PGND RT OVP SYNC ILIM IA OUT IA- IA+ ISINE EA OUT EA- VRMS SOFT START N/C
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
GND CT VREF VCC OUT PGND RT OVP SYNC N/C
TOP VIEW TOP VIEW
Pin Description
Pin Number 18-Pin DIP 1 2 3 4 5 6 7 8 9 10 11 20-Pin SOIC 1 2 3 4 5 6 7 8 9 12 13 Name ILIM IA OUT IA- IA+ ISINE INV VRMS SOFT START SYNC OVP Function Peak cycle-by-cycle current limit input Output and compensation node of the average current error amplifier Inverting input of the average current error amplifier Non-Inverting input of the average current error amplifier and output of the gain modulator Gain modulator input Inverting input to error amplifier Input for average line voltage compensation Normally connected to soft start capacitor Oscillator synchronization input Inhibits output pulses when the voltage at this pin exceeds 5V. Also, when the voltage at this pin is less than 0.7V, the IC goes into low current shut-down mode. Timing resistor for the oscillator Return for the high current totem pole output High current totem pole output Positive supply for the IC Buffered output for the 5V voltage reference Timing capacitor for the oscillator. Analog signal ground
EA OUT Output of output voltage error amplifier
12 13 14 15 16 17 18
14 15 16 17 18 19 20
RT PWR GND OUT VCC VREF CT GND
2
REV. 1.0.2 6/19/01
PRODUCT SPECIFICATION
ML4821
Absolute maximum ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter Supply Current (ICC) OUT Current, Source or Sink Output Energy (capacitive load per cycle) ISINE Input Current EA OUT Source Current Oscillator Charge Current Input Voltage Junction Temperature Storage Temperature Range Lead Temperature (Soldering 10 sec.) Thermal Resistance (JA) Plastic DIP Plastic SOIC -65 GND -0.3V Min Max 35 1.0 5 1.2 50 2 5.5 150 150 260 75 95 Units mA A J mA mA mA V C C C C/W C/W
Operating Conditions
Temperature Range ML4821CX Min 0 Max 70 Units C
Unless otherwise specified, RT = 6.2k, CT = 720pF, TA = Operating Temperature Range, VCC = 15V (Notes 1 & 2). Parameter Oscillator Initial accuracy Voltage stability Temperature stability Total Variation Ramp Valley to Peak RT Voltage Discharge Current SYNC Input Threshold Reference Output Voltage Line regulation Load regulation Temperature stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current line, load, temp 10Hz to 10kHz TA = 125C, 1000 hrs VREF = 0V -30 4.9 50 5 -85 25 -180 TA = 25C, IO = 1mA 12V < VCC < 24V 1mA < IO < 20mA 4.95 5.00 2 2 .4 5.1 5.05 10 15 V mV mV % V V mV mA CT= 2V, RT = Open Line, Temperature 85 4.7 4.8 7.8 1.5 5.2 5.0 8.4 2.0 TA = 25C 12V < VCC < 18V 90 100 1 2 115 5.6 5.2 9.3 3.0 110 kHz % % kHz V V mA V Conditions Min. Typ. Max. Units
Electrical Characteristics
REV. 1.0.2 6/19/01
3
ML4821
PRODUCT SPECIFICATION
Electrical Characteristics (continued) Unless otherwise specified, RT = 6.2k, CT = 720pF, TA = Operating Temperature Range, VCC = 15V (Notes 1 & 2).
Parameter Voltage Error Amplifier Input Offset Voltage Input Bias Current Open Loop Gain PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth Soft Start Charge Current Current Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain PSRR Output Voltage Low Output Voltage High Input Common Mode Range Gain Modulator Gain VINV = 4.8V, VRMS = 0V VINV = 4.8V, VRMS = 1.75V VINV = 4.8V, VRMS = 2.6V VINV = 4.8V, VRMS = 5.2V VINV = 5.2V, VRMS = 5.2V VINV = 4.8V, ISINE = 500A, VRMS = 1.75V 360 0.75 3.1 1.25 0.22 1.2 3.88 1.75 0.38 -2 395 1.3 4.5 2.15 0.50 -4 420 A A 2 < EA OUT < 7V 12V < VCC < 24V IOL = 300A IOH = -10mA 7.0 -0.3 80 65 100 85 0 7.5 2.5 0.5 -5 0 -0.15 5 -1 400 mV A nA dB dB V V V VPIN9 = 4V -22 2 < EA OUT < 6V 12V < VCC < 24V EA OUT = 4V, INV = 5.5V EA OUT = 4.0V, INV = 4.8V IPIN6 = -5mA, VPIN7 = 4.8V IPIN6 = 0, EA- = 5.5V 60 70 300 -10 7.0 0 -50 75 100 500 -30 7.5 0 1.0 -38 -50 0.5 -15 -800 mV nA dB dB A mA V V MHz A Conditions Min. Typ. Max. Units
Output Current Output Current Limit ILIM Comparator Input Offset Voltage Input Bias Current OVP Comparator Input Offset Voltage Hysteresis Input Bias Current Propagation Delay Shutdown Threshold PWM Comparator Input Common Mode Range Propagation Delay
+15 -100 Output Off Output On -25 85 105 -0.3 150 0.4 0 150 0.7 1.0 8 -200 5 130 -3
mV A mV mV A ns V V ns
4
REV. 1.0.2 6/19/01
PRODUCT SPECIFICATION
ML4821
Electrical Characteristics (continued) Unless otherwise specified, RT = 6.2k, CT = 720pF, TA = Operating Temperature Range, VCC = 15V (Notes 1 & 2).
Parameter Output Output Voltage Low Output Voltage High Output Voltage Low in UVLO Output Rise/Fall Time Undervoltage Lockout Start-up Threshold Shut-Down Threshold VREF Good Threshold Supply Supply Current Internal Shunt Zener Voltage Start-up, VCC = 14V, TA = 25C Operating, TA = 25C ICC = 35mA 25 0.6 26 27 1.2 32 35 mA mA V 14.5 8.5 4.4 16.5 11.0 V V V IOUT = 20mA IOUT = 200mA IOUT = -20mA IOUT = -200mA IOUT = -5mA, VCC = 8V CL = 1000pF 13 12 0.1 1.6 13.5 13.4 0.1 50 0.8 0.4 2.4 V V V V V ns Conditions Min. Typ. Max. Units
Notes: 1. Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. 2. VCC is raised above the start-up threshold first to activate the IC, then returned to 15V 3. Gain Modulator gain is defined as: I OUTIA+ -----------------------I INEAOUT
REV. 1.0.2 6/19/01
5
ML4821
PRODUCT SPECIFICATION
Functional Description
Oscillator
The ML4821 oscillator charges the external capacitor connected to CT with a current equal to 2.5/RT. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. The oscillator period can be described by the following relationship:
TOSC = TRAMP + TDISCHARGE
VOLTAGE and Current ERROR Amplifiers
The ML4821 voltage error amplifier is a high open loop gain, wide bandwidth amplifier with a class A output. The soft start circuit controls the input to this amplifier for closed loop soft start operation. The current error amplifier (IA) is similar to the voltage error amplifier but is designed for very low offsets to allow the selection of a low value resistor for RSENSE.
Output Driver Stage
The ML4821 Output Driver is a 1A peak output high speed totem pole circuit designed to quickly drive capacitive loads, such as power MOSFET gates. The driver circuit's output voltage is internally limited to 17V.
where:
TRAMP = C(Ramp Valley to Peak) / (IRT/2)
and:
TDISCHARGE = C(Ramp Valley to Pk) / (8.4mA - IRT/2)
CLOCK tD RAMP PEAK CT RAMP VALLEY
Gain Modulator
The ML4821 gain modulator responds linearly to current injected into the ISINE pin, and in an inverse-square fashion to voltage on the VRMS pin. At very low voltages on the VRMS pin, the gain modulator enforces a power limit, or "brownout protection", upon the overall PFC circuit (Figures 6 and 7). The rectified line input sine wave is converted to a current for the ISINE input via a dropping resistor. In this way, most ground noise produces an insignificant effect on the reference to the PWM comparator. This gives the ML4821 a high degree of immunity to the disturbances common in highpower switching circuits.
The ML4821 oscillator includes a SYNC input for synchronizing to an external frequency source. A positive pulse on this pin of 2V (typ) resets the oscillators comparator and initiates a discharge cycle for CT. The RT and CT component values which set the ML4821 oscillator frequency should be selected to produce a lower frequency than the external frequency source.
RT RT
VREF IRT IRT 2 FREQUENCY (kHz)
1000
CT
+ -
150pF 100
CT
8.4mA
330pF
Q1
1nF 680pF
470pF
SYNC 2k 1k
10 Q2 0 10 20 RT (k) 30 40 50
Figure 2. Oscillator Timing Resistance vs. Frequency Figure 1. Oscillator Block Diagram
6
REV. 1.0.2 6/19/01
PRODUCT SPECIFICATION
ML4821
7 +8V
AVOL, OPEN-LOOP VOLTAGE GAIN (dB)
INV
100 80 GAIN 60 40 PHASE 20 0 -20 10 100 1.0k 10k 100k f, FREQUENCY (Hz) 1.0M VCC = 15V VO = 1.0V TO 5.0V RL = 100k TA= 25C
0 -30 60 90 120 150 180 10M PHASE (DEGREES)
-
+8V VREF
+
EA OUT 6
S.S 9
6.2k
Figure 3. Error and Current Amplifier Configuration
Figure 4. Error Amplifier Open-loop Gain and Phase vs. Frequency.
0.5
0 VCC .0 2.0 TA = 25C
SOURCE SATURATION
OPERATING BOUNDRY
VCC = 15V 80s PULSED LOAD
0.4
DESIGN FOR BROWNOUT
DESIGN FOR NORMAL OPERATIONS THIS IS THE MINIMUM OPERATING VOLTAGE POINT
TA = -55C K 3.0 TA = -55C 2.0 .0 0 0 200 400 600 800 IO, OUTPUT LOAD CURRENT (mA) SINK SATURATION GND TA = 25C
0.3
0.2
0.23
THIS GAIN CURVE TAKES OUT THE 1/(VIN)2 DEPENDENCY OF THE VOLTAGE CONTROL LOOP
0.1
0 0 1 2
85VAC
3
120VAC
4 VRMS
5
220VAC
6
7
Figure 5. Output Saturation Voltage vs. Output Current.
Figure 6. K-factor. Gain Modulator gain with respect to the voltage at VRMS.
The output of the gain modulator is a current which appears on IA+ to form the reference for the current error amplifier and is given as:
IGM = K x ISINE x (VEA - 0.8)
where: ISINE is the current in the dropping resistor, VEA is the output of the error amplifier and K is a constant determined by the VRMS input.
2.5 I GM ( MAX ) = ------RT
Figure 6 shows the gain adjustor (K) with respect to the voltage at VRMS. The curve has been separated in two parts. The right hand part is for operation under normal conditions in the voltage range from minimum line voltage to maximum line voltage (90VAC to 260VAC). 85VAC on the curve has been chosen to account for tolerances. Under normal operating conditions as input voltage decreases the gain increases compensating for the drop in the loop gain. Under brownout conditions (below 85VAC) the gain decreases to limit the amount of current that is drawn from the line thus preventing an overload condition. This is a very useful feature since in many cases the load for a PFC is a constant power load. The input current has to go high to compensate for a drop in the input voltage.
The output current of the gain modulator is limited to: This sets the system current limit.The multiplier output current is converted into the reference voltage for the current (IA) amplifier through a resistor to ground on IA+.
REV. 1.0.2 6/19/01
7
ML4821
PRODUCT SPECIFICATION
Under Voltage Lockout, OVP and Current Limit
On power-up the ML4821 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 9V, the UVLO condition is imposed. During the UVLO condition, the VREF pin is "off", making it usable as a "flag" for starting up a down-stream PWM converter.
OVP, Shutdown, and IC Bias
When the input to the OVP comparator exceeds VREF, the output of the ML4821 is inhibited. The OVP input also functions as a "sleep" input, putting the IC into the low quiescent UVLO state when the OVP pin is pulled below 0.7V.
MULTIPLIER OUTPUT CURRENT (A)
500 RT = 5k VRMS = 3V 400
5.5 E/A OUTPUT VOLTAGE
- +
ENABLE VREF
4.4V
4.5 300 3.5 200 2.5 100 1.5 0 0 100 200 300 400 SINE INPUT CURRENT (A) 1.0 500
LOGIC POWER VREF 16
9V
- +
INTERNAL BIAS
VCC
15
Figure 7. Gain Modulator Linearity.
Figure 8. Under-Voltage Lockout Block Diagram.
VREF, REFERENCE VOLTAGE CHANGE (mV)
40 ICC SUPPLY CURRENT (mA)
0 VCC = 15V -4.0 -8.0
30
20 TA = 25C 10
-12 TA = -55C -16 TA = 125C
-20
TA = 25C
0 0 10 20 30 VCC SUPPLY VOLTAGE (V)
-24 0 20 40 60 80 100 120 IREF, REFERENCE SOURCE CURRENT (mA)
Figure 9. Total Supply Current vs. Supply Voltage.
Figure 10. Reference Load Regulation.
8
REV. 1.0.2 6/19/01
PRODUCT SPECIFICATION
ML4821
Off-line Start-up and Bias Supply Generation
The circuit in Figure 11 supplies VCC power to the ML4821. Start-up current is delivered via R10. The IC starts when VCC reaches 15.5V. After that time running power is delivered through the tap on L1. The configuration shown delivers a voltage proportional to the PFC output bus voltage.
R10 39k 2W
TO B+
L1 NP NS
1F 1000F 1F
TO IC PIN 15
NP NS
VOUT 14V
Figure 11. Bias and Start-up Circuit.
REV. 1.0.2 6/19/01
9
ML4821
PRODUCT SPECIFICATION
F1 5A, 250V D1 AC IN 90-264 VAC C1 1F D2
D1 1N5406 L1 + D3 D4 D7 1N4934 C12 1F C13 1F D8 1N4934 R7 560k D10 MUR850 C14 470F C14 470F DC OUT 382V
R10 39k
C19 270F 450V
-
R11 8.2k
R5 2k
R8 910k
ML4821
1 2 ILIM IA OUT IA- IA+ ISINE EA OUT EA- VRMS GND CT VREF VCC OUT PGND RT OVP 18 17 16 15 14 13 12 11 10
R22 7.3
R6 2.7k R13 20k
3 4 5
R9 91k
C2 120pF
6 7
R20 825k
C5 1.5nF
8 9
C3 0.1F
SOFT START SYNC
R19 10.2k
R18 825k
D5 1N5406
R12 2.7k C4 1.5nF
R14 91k
C6 43nF R21 6.2k
C8 C10 0.1F
C11 750pF
R17 10.5k
D6 1N5406
R1 0.25
R15 27k
C7 0.47F
Figure 12. 200W Output PFC Circuit
10
REV. 1.0.2 6/19/01
PRODUCT SPECIFICATION
ML4821
Mechanical Dimensions inches (millimeters)
Package: P18 18-Pin PDIP
0.890 - 0.910 (22.60 - 23.12) 18
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.045 MIN (1.14 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S20 20-Pin SOIC
0.498 - 0.512 (12.65 - 13.00) 20
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE 0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.007 - 0.015 (0.18 - 0.38)
REV. 1.0.2 6/19/01
11
ML4821
PRODUCT SPECIFICATION
Ordering Information
Part Number ML4821CP ML4821CS Temperature Range 0C to 70C 0C to 70C Package 18-Pin PDIP (P18) 20-Pin SOIC (S20)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
6/19/01 0.0m 003 Stock#DS30004821 " 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

▲Up To Search▲

Price & Availability of ML4821

	To Download ML4821 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .